The present invention relates to a multiprocessor system having a plurality of instruction processors, and more particularly to a multiprocessor system which receives multi-level I/O interrupts from a common I/O device to select those of a plurality of instruction processors which process respective I/O interrupts.
When an I/O interrupt is to be processed in a multiprocessor system having a plurality of instruction processors, an I/O interrupt can be selected from not only the instruction processor which has energized the channel through which the I/O interrupt has been issued, but also from any instruction processor out of the plurality of instruction processors. An example thereof is disclosed in U.S. Pat. No. 4,271,468. In such a system, the I/O interrupt is processed in the following manner. An I/O interrupt request from a channel controller is temporarily held in a system controller, which then inquires to each instruction processor whether or not it can accept the interrupt request. The instruction processors each indicate whether they can accept the interrupt request to the system controller, which, after receipt of replies from all instruction processors, selects an optimum instruction processor and causes it to process the interrupt. This will be explained in more detail with reference to a system configuration shown in FIG. 1.
FIG. 1 shows a configuration of a multiprocessor system. Numerals 1A and 1B denote instruction processors (hereinafter referred to as IP0 and IP1), numeral 2 denotes a system controller (SC), numeral 3 denotes a main storage (MS), numeral 4 denotes a channel controller (CHC), numeral 5 denotes an I/O controller (IOC), numeral 6 denotes an I/O device (I/O), numeral 21 denotes an interrupt pending register, and numeral 31 denotes an interrupt queue for one of a plurality of levels .theta..sub.0 -.theta..sub.7.
In the multiprocessor system shown in FIG. 1, IP0 and IP1 share MS 3 and CHC 4 through SC 2, one IOC 5 is connected to each channel (CH) of CHC 4, and a plurality of I/O's are connected to each IOC 5. The interrupt queue 31 is provided in MS 3 to store pending I/O interrupt requests as queues .theta..sub.0 -.theta..sub.7 for respective levels. The interrupt pending register 21 which indicates whether the queues for the respective levels in MS 3 are empty or not is provided in the SC 2. Bits 0-7 of the register 21 indicate empty or not empty states of the queues .theta..sub.0 -.theta..sub.7.
When an I/O interrupt request is issued from CH 4 to SC 2, SC 2 registers the interrupt request in the interrupt queue .theta..sub.i of the corresponding level in MS 3. If the interrupt queue .theta..sub.i is empty and it is to register the interrupt request for the first time, a corresponding bit of the interrupt pending register 21 in SC 2 is set to "1". If one or more interrupt requests have been registered in the queue .theta..sub.i, the corresponding bit of the interrupt pending register 21 has been set to "1" and no further change is made. SC 2 sends the content of the interrupt pending register 21 simultaneously to IP0 and IP1. If IP0 and IP1 are in a state to be able to accept the interrupt, they send accept signals and highest order non-masked queue identifier signals to SC 2. If IP0 or IP1 is in a wait state, it also sends a WAIT signal to SC 2. SC 2 responds to the response signals from IP0 and IP1 as follows.
(1) If only one IP sends back accept signal and the other IP does not send it back, SC 2 causes the former IP to handle the interrupt request. PA0 (2) If two IP's send back accept signals and the levels of the interrupt queues are not equal, SC 2 causes both IP's to handle interrupt request. PA0 (3) If two IP's send back accept signals and the levels of the interrupt queues are equal; and
(A) if none of the two IP's is in the wait state or if both IP's are in the wait state, SC 2 selects one of the IP's in a predetermined priority order and causes the selected IP to handle the interrupt request, or PA1 (B) if only one IP is in the wait state, SC 2 causes the IP which is in the wait state to handle the interrupt request.
In U.S. Pat. No. 4,644,465, an interrupt controller in the SC holds I/O interrupt control data of the respective IP's, and selects an appropriate IP without corresponding with the IP's to cause the selected IP to handle the I/O interrupt request.
In the prior art I/O interrupt handling system, if an IP in the wait state is present, that IP is selected for handling the interrupt request in order to enhance system performance.
However, in the prior art system, even if the IP is not in the wait state, it sends back the accept signal to the SC in one of the following cases, and if it is selected by the SC, it handles the interrupt request.
(1) An I/O interrupt request is issued at a break of instructions and there is no higher priority interrupt factor than the I/O interrupt.
(2) An I/O interrupt request is issued during execution of instructions, such as an integrated array processor (IAP) instruction or a longer (MVCL) instruction, there is no higher priority interrupt factor than the I/O interrupt and an instruction which permits acceptance of the interrupt is being executed.
The MVCL instruction provides for transfer of a specified length of data from a second address of the MS to a first address. The IAP instruction calls for a vector operation not in an independent array processor, but in an IP. There may be first, second and third operands. In such a case, an operation result involving the second and third operands is stored in a location specified by the first operand. The operation is iterated as many times as the number of elements specified by the instruction.
Since the execution time for the IAP instruction or MVCL instruction may be long, the IP permits acceptance of an interrupt request during the execution of such instruction. After the interrupt request has been handled, the execution of the instruction is resumed. Since such instruction is executed with prefetching of operands in the IP, the prefetched operands are invalidated and save and restore operations of registers are required if the interrupt request is accepted in the course of execution of the instruction and the interrupting program is executed. As a result, the overall system performance is lowered.